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1 features ? serial eeprom family for configuring altera flex ? devices ? simple interface to sram fpgas ? ee programmable 512k and 1m-bit serial memories designed to store configuration programs for field programmable gate arrays (fpgas) ? cascadable read back to support additional configurations or future higher-density arrays ? low-power cmos eeprom process ? programmable reset polarity ? available in the space-efficient surface-mount plcc package ? in-system programmable via 2-wire bus ? emulation of atmels at24cxxx serial eeproms ? available in 3.3v 10% lv and 5v 5% c versions ? system-friendly ready pin description the at17c512a/010a and at17lv512a/010a (high-density at17a series) fpga configuration eeproms (configurators) provide an easy-to-use, cost-effective con- figuration memory for programming altera flex ? devices. the at17a series is packaged in the popular 20-pin plcc. the at17a series family uses a simple serial- access procedure to configure one or more fpga devices. the at17a series organi- zation supplies enough memory to configure one or multiple smaller fpgas. using a feature of the at17a series, the user can select the polarity of the reset function by programming four eeprom bytes. the at17a parts generate their own internal clock and can be used as a system master for loading the fpga devices. the atmel devices also support a system-friendly ready pin and a write protect mechanism. the ready pin is used to simplify system power-up considerations. the wp1 pin is used to protect part of the configurator memory during in-system programming. the at17a series configurators can be programmed with industry-standard program- mers, or atmels atdh2200e programming kit. fpga configuration eeprom memory 512k and 1m altera pinout at17c512a at17lv512a at17c010a AT17LV010A rev. 0974bC07/99 pin configurations plcc 4 5 6 7 8 18 17 16 15 14 dclk wp1 nc nc oe ser_en nc nc ready nc 3 2 1 20 19 9 10 11 12 13 ncs gnd nc (a2) ncasc nc nc data nc vcc nc
at17c/lv512a/010a 2 block diagram device configuration the control signals for the configuration eepromCncs, oe, and dclkCinterface directly with the fpga device control signals. all fpga devices can control the entire configuration process and retrieve data from the configura- tion eeprom without requiring an external intelligent controller. the configuration eeproms oe and ncs pins control the tri-state buffer on the data output pin and enable the address counter and the oscillator. when oe is driven low, the configuration eeprom resets its address counter and tri-states its data pin. the ncs pin also controls the out- put of the at17a series configurator. if ncs is held high after the oe reset pulse, the counter is disabled and the data output pin is tri-stated. when ncs is driven low, the counter and the data output pin are enabled. when oe is driven low again, the address counter is reset and the data output pin is tri-stated, regardless of the state of the ncs. when the configurator has driven out all of its data and ncasc is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. the ready pin is available as an open-collector indicator of the devices reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. this document discusses the epf10k device interface. for more details or information on other altera applications, please reference the at17a series conversions from altera fpga serial configuration memories application note. eeprom cell matrix row decoder column decoder tc ncs dclk ready oe ncasc (a2) data bit counter osc osc control programming data shift register programming mode logic row address counter power on reset ser_en wp1
at17c/lv512a/010a 3 fpga device configuration fpga devices can be configured with an at17a series eeprom as shown in figure 1. the at17a series device stores configuration data in its eeprom array and clocks the data out serially with its internal oscillator. the oe, ncs, and dclk pins supply the control signals for the address counter and the output tri-state buffer. the at17a series device sends a serial bitstream of configuration data to its data pin, which is connected to the data0 input pin on the fpga device. when configuration data for an fpga device exceeds the capacity of a single at17a series device, multiple at17a series devices can be serially linked together (figure 2). when multiple at17a series devices are required, the ncasc and ncs pins provide handshaking between the cascaded eeproms. the position of an at17a series device in a chain deter- mines its operation. the first at17a series device in a configurator chain is powered up or reset with ncs low and is configured for the fpga devices protocol. this at17a series device supplies all clock pulses to one or more fpga devices and to any downstream at17a series configurator during configuration. the first at17a series configurator also provides the first stream of data to the fpga devices during multi-device configuration. once the first at17a series device finishes sending configuration data, it drives its ncasc pin low, which drives the ncs pin of the second at17a series device low. this activates the second at17a series device to send configuration data to the fpga device. the first at17a series device clocks all subsequent at17a series devices until configuration is complete. once all configuration data is transferred and ncs on the first at17a series device is driven high by conf_done on the fpga devices, the first at17a series device clocks 16 additional cycles to initialize the fpga device before going into zero-power (idle) state. if ncs on the first at17a series device is driven high before all configuration data is transferredCor if the ncs is not driven high after all configu- ration data is transferredC nstatus is driven low, indicating a configuration error. the ready pin is available as an open-collector indicator of the devices reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. it can be used to hold the fpga device in reset while it is completing its power-on reset but it cannot be used to effectively delay configuration (i.e., the output is released well before the system vcc has stabilized). figure 1. configuration with a single at17a series configurator notes: 1. 1.0 k w resistors used unless otherwise specified. 2. applicable to epf6k. 3. use of the ready pin is optional. 4. introducing a rc delay to the input of nconfig is recommended to ensure that vcc (5v/3.3v) is reached before configuration begins. (nconfig can instead be connected to an active low system reset signal.) 5. reset polarity of eeprom must be set active low (oe active high). msel1 nstatus msel0 conf_done data0 dclk nconfig epf10k at17c512a/010a at17lv512a/010a gnd oe ncs data dclk nce vcc vcc vcc ready
at17c/lv512a/010a 4 figure 2. configuration with multiple at17a series configurators notes: 1. 1.0 k w resistors used unless otherwise specified. 2. use of the ready pin is optional. 3. introducing a rc delay to the input of nconfig is recommended to ensure that vcc (5v/3.3v) is reached before configuration begins. (nconfig can instead be connected to an active low system reset signal.) 4. reset polarity of eeprom must be set active low (oe active high). at17a series reset polarity the at17a series configurator allows the user to program the reset polarity as either reset/oe or reset /oe. for more details, please reference the programming specifi- cation for atmels fpga configuration eeproms application note. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be programmed by the 2-wire serial interface. the programming is done at vcc supply only. programming super voltages are generated inside the chip. see the programming specification for atmels configuration eeproms application note for fur- ther information. the at17 a-series parts are read/write at 5v nominal. the at17lv a-series parts are read/write at 3.3v nominal. standby mode the at17a series configurator enters a low-power standby mode whenever ncs is asserted high. in this mode, the configuration consumes less than 0.5 ma of cur- rent at 5v. the output remains in a high-impedance state regardless of the state of the oe input. msel1 nstatus msel0 conf_done data0 dclk nconfig epf10k at17c512a/010a at17lv512a/010a device 1 gnd vcc vcc oe ncs ncasc data dclk at17c512a/010a at17lv512a/010a device 2 oe ncs data dclk vcc ready ready nce
at17c/lv512a/010a 5 pin configurations 20 plcc pin name i/o description 2 data i/o three-state data output for configuration. open-collector bi-directional pin for programming. 4 dclk i/o clock output or clock input. rising edges on dclk increment the internal address counter and present the next bit of data to the data pin. the counter is incremented only if the oe input is held high, the ncs input is held low, and all configuration data has not been transferred to the target device (otherwise, as the master device, the dclk pin drives low). 5 wp1 i write protect (1). used to protect portions of memory during programming. disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. see programming specifications for details. 8 oe i output enable (active high) and reset (active low) when ser_en is high. a low logic level resets the address counter. a high logic level (with ncs low) enables data and permits the address counter to count. in the mode, if this pin is low (reset), the internal oscillator becomes inactive and dclk drives low. the logic polarity of this input is programmable and must be programmed active high (reset active low) by the user during programming for altera applications. 9 ncs i chip select input (active low). a low input (with oe high) allows dclk to increment the address counter and enables data to drive out. if the at17a series is reset with ncs low, the device initializes as the first (and master) device in a daisy-chain. if the at17a series is reset with ncs high, the device initializes as a subsequent at17a series device in the chain. 10 gnd ground pin. a 0.2 f decoupling capacitor should be placed between the vcc and gnd pins. 12 ncasc o cascade select output (active low). this output goes low when the address counter has reached its maximum value. in a daisy-chain of at17a series devices, the ncasc pin of one device is usually connected to the ncs input pin of the next device in the chain, which permits dclk from the master configurator to clock data from a subsequent at17a series device in the chain. a2 i device selection input, a2. this is used to enable (or select) the device during programming, (i.e., when ser_en is low; please refer to the programming specification application note for more details). 15 ready o open collector reset state indicator. driven low during power-up reset, released (tri-stated) when power-up is complete. (recommend a 4.7 k w pull-up on this pin if used). 18 ser_en i serial enable must be held high during fpga loading operations. bringing ser_en low, enables the 2-wire serial programming mode. 20 vcc +3.3v/+5v power supply pin absolute maximum ratings* operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other condi- tions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +7.0v maximum soldering temp. (10 sec @ 1/16 in.)..............260 c esd (r zap = 1.5k, c zap = 100 pf) ................................ 2000v
at17c/lv512a/010a 6 operating conditions symbol description at17cxxxa at17lvxxxa units min/max min/max v cc commercial supply voltage relative to gnd -0 c to +70 c 4.75/5.25 3.0/3.6 v industrial supply voltage relative to gnd -40 c to +85 c 4.5/5.5 3.0/3.6 v military supply voltage relative to gnd -55 c to +125 c 4.5/5.5 3.0/3.6 v
at17c/lv512a/010a 7 dc characteristics v cc = 5v 5% commercial / 5v 10% ind./mil. symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = -4 ma) commercial 3.86 v v ol low-level output voltage (i ol = +4 ma) 0.32 v v oh high-level output voltage (i oh = -4 ma) industrial 3.76 v v ol low-level output voltage (i ol = +4 ma) 0.37 v v oh high-level output voltage (i oh = -4 ma) military 3.7 v v ol low-level output voltage (i ol = +4 ma) 0.4 v i cca supply current, active mode (at fmax) 10 ma i l input or output leakage current (v in = v cc or gnd) -10 10 a i ccs supply current, standby mode at17c512a/010a commercial 0.5 ma industrial/military 0.5 ma dc characteristics v cc = 3.3v 10% symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v v oh high-level output voltage (i oh = -2 ma) industrial 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v v oh high-level output voltage (i oh = -2 ma) military 2.4 v v ol low-level output voltage (i ol = +2.5 ma) 0.4 v i cca supply current, active mode (at fmax) 5 ma i l input or output leakage current (v in = v cc or gnd) -10 10 a i ccs supply current, standby mode commercial 100 a industrial/military 100 a
at17c/lv512a/010a 8 ac characteristics ac characteristics when cascading ncs oe dclk data t sce t lc t hc t oe t ce t cac t oh t hoe t hce t sce t df t oh oe ncs dclk data ncasl t cdf t ock last bit t oce t ooe t oce first bit
at17c/lv512a/010a 9 . notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady state active levels. ac characteristics for at17c512a/010a v cc = 5v 5% commercial / v cc = 5v 10% ind./mil symbol description commercial industrial/military (1) units min max min max t oe (2) oe to data delay 30 35 ns t ce (2) ncs to data delay 45 45 ns t cac (2) dclk to data delay 50 55 ns t oh data hold from ncs, oe, or dclk 0 0 ns t df (3) ncs or oe to data float delay 50 50 ns t lc dclk low time slave mode 20 20 ns t hc dclk high time slave mode 20 20 ns t sce ncs setup time to dclk (to guarantee proper counting) 20 25 ns t hce ncs hold time from dclk (to guarantee proper counting) 00ns t loe oe low time (guarantees counter is reset) 20 20 ns f max max input clock frequency slave mode 15 15 mhz t lc dclk low time master mode 30 250 30 250 ns t hc dclk high time master mode 30 250 30 250 ns ac characteristics for at17c512a/010a when cascading v cc = 5v 5% commercial / v cc = 5v 10% ind./mil. symbol description commercial industrial/military (1) units min max min max t cdf (3) dclk to data float delay 50 50 ns t ock (2) dclk to ncasc delay 35 40 ns t oce (2) ncs to ncasc delay 35 35 ns t ooe (2) oe to ncasc delay 30 30 ns f max max input clock frequency 12.5 12.5 mhz
at17c/lv512a/010a 10 . notes: 1. preliminary specifications for military operating range only. 2. ac test load = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady state active levels. ac characteristics for at17lv512a/010a v cc = 3.3v 10% commercial / v cc = 3.3v 10% ind./mil. symbol description commercial industrial/military (1) units min max min max t oe (2) oe to data delay 50 55 ns t ce (2) ncs to data delay 55 60 ns t cac (2) dclk to data delay 60 65 ns t oh data hold from ncs, oe, or dclk 0 0 ns t df (3) ncs or oe to data float delay 50 50 ns t lc dclk low time slave mode 25 25 ns t hc dclk high time slave mode 25 25 ns t sce ncs setup time to dclk (to guarantee proper counting) 35 40 ns t hce ncs hold time from dclk (to guarantee proper counting) 00ns t loe oe low time (guarantees counter is reset) 20 20 ns f max max input clock frequency slave mode 15 10 mhz t lc dclk low time master mode 30 300 30 300 ns t hc dclk high time master mode 30 300 30 300 ns v rdy ready pin open collector voltage 1.2 2.4 1.2 2.4 v ac characteristics for at17lv512a/010a when cascading v cc = 3.3v 10% commercial / v cc = 3.3v 10% ind./mil. symbol description commercial industrial/military (1) units min max min max t cdf (3) dclk to data float delay 50 50 ns t ock (2) dclk to ncasc delay 50 55 ns t oce (2) ncs to ncasc delay 35 40 ns t ooe (2) oe to ncasc delay 35 35 ns f max max input clock frequency slave mode 12.5 10 mhz
at17c/lv512a/010a 11 notes: 1. use 512k density parts to replace altera epc1441. 2. use 1m density parts to replace altera epc1. ordering information - 5v devices memory size ordering code package operation range 512k (1) at17c512a-10jc 20j commercial (0 c to 70 c) at17c512a-10ji 20j industrial (-40 c to 85 c) 1m (2) at17c010a-10jc 20j commercial (0 c to 70 c) at17c010a-10ji 20j industrial (-40 c to 85 c) ordering information - 3.3v devices memory size ordering code package operation range 512k (1) at17lv512a-10jc 20j commercial (0 c to 70 c) at17lv512a-10ji 20j industrial (-40 c to 85 c) 1m (2) AT17LV010A-10jc 20j commercial (0 c to 70 c) AT17LV010A-10ji 20j industrial (-40 c to 85 c) package type 20j 20-lead, plastic j-leaded chip carrier (plcc)
at17c/lv512a/010a 12 packaging information 20j , 20-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 aa
? atmel corporation 1999. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the companys standard war- ranty which is detailed in atmels terms and conditions located on the companys web site. the company assumes no responsibilit y for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmels pr oducts are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel u.k., ltd. coliseum business centre riverside way camberley, surrey gu15 3yl england tel (44) 1276-686-677 fax (44) 1276-686-697 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 application support hotline: 1-(408) 436-4119 e-mail: configurator@atmel.com faq: accessible from web site fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 0974bC07/99/xm marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others.

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